1 UT54ACTS74E dual d flip-flops with clear & preset july, 2013 datasheet www.aeroflex.com/logic features ? ???? m crh cmos process - latchup immune ? high speed ? low power consumption ? wide power supply operating range from 3.0v to 5.5v ? available qml q or v processes ? 14-lead flatpack ? UT54ACTS74E-smd- 5962-96535 description the UT54ACTS74E contains two independent d-type positive triggered flip-flops. a low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. when preset and clear are inactive (high), data at the d input meeting the setup time re quirement is transferred to the outputs on the positive-going edge of the clock pulse. follow- ing the hold time interval, data at the d input may be changed without affecting the le vels at the outputs. the device is characterized over full hirel temperature range of -55 ? c to +125 ? c. function table note: 1. the output levels in th is configuration are not gua ranteed to meet the mini- mum levels for v oh if the lows at preset and clear are near v il maximum. in addition, this configur ation is nonstable; that is, it will not persist when either preset or clear return s to its inactive (high) level. pinouts 14-lead flatpack topview logic symbol inputs output pre clr clk d q q l h x x h l h l x x l h l l x x h 1 h 1 h h ? h h l h h ? l l h h h l x q o q o 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd clr2 d2 clk2 pre2 q2 q2 clr1 d1 clk1 pre1 q1 q1 v ss q1 (5) (6) q1 q2 (9) (8) q2 (4) pre1 (3) clk1 (2) d1 (1) clr1 (10) pre2 (11) clk2 (12) d2 (13) clr2 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. s c1 d1 r
2 logic diagram pre clr clk q q d
3 operational environment 1 notes: 1. logic will not latchup during radiation expo sure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational s ections is not recommended. ex posure to absolute maximum ra ting conditions for extended periods may affect device reliability. 2. per mil-std-883, method 1012.1, section 3.4.1, p d = (t j(max) - t c(max) ) / ? jc recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -0.3 to v dd +0.3 v t stg storage temperature range -65 to +150 ? c t j maximum junction temperature +175 ? c t ls lead temperature (soldering 5 seconds) +300 ? c ? jc thermal resistance junction to case 15.5 ? c/w i i dc input current ? 10 ma p d 2 maximum package po wer dissipation permitted @ t c = +125 o c 3.2 w symbol parameter limit units v dd supply voltage 3.0 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 ? c
4 dc electrical characteristics for the UT54ACTS74E 7 ( v dd = 3.0v to 5.5v; v ss = 0v 6 ; -55 ? c < t c < +125 ? c) symbol description condition min max unit v il1 low-level input voltage 1 v dd from 4.5v to 5.5v 0.8 v v il2 low-level input voltage 1 v dd from 3.0v to 3.6v 0.8 v v ih1 high-level input voltage 1 v dd from 4.5v to 5.5v 0.5 v dd v v ih2 high-level input voltage 1 v dd from 3.0v to 3.6v 2.0 v i in input leakage current v in = v dd or v ss -1 1 ? a v ol1 low-level output voltage 3 i ol = 8ma v dd = 4.5v to 5.5v 0.4 v v ol2 low-level output voltage 3 i ol = 6ma v dd = 3.0v to 3.6v 0.4 v v oh1 high-level output voltage 3 i oh = -8ma v dd from 4.5v to 5.5v 0.7 v dd v v oh2 high-level output voltage 3 i oh = -6ma v dd from 3.0v to 3.6v 2.4 v i os1 short-circuit output current 2 ,4 v o = v dd and v ss v dd from 4.5v to 5.5v -200 200 ma i os2 short-circuit output current 2 ,4 v o = v dd and v ss v dd from 3.0v to 3.6v -100 100 ma i ol1 low level output current 9 v in = v dd or v ss v ol = 0.4v v dd from 4.5v to 5.5v 8 ma i ol2 low level output current 9 v in = v dd or v ss v ol = 0.4v v dd from 3.0v to 3.6v 6 ma i oh1 high level output current 9 v in = v dd or v ss v oh = v dd -0.4v v dd from 4.5v to 5.5v -8 ma i oh2 high level output current 9 v in = v dd or v ss v oh = v dd -0.4v v dd from 3.0v to 3.6v -6 ma
5 notes: 1. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schm itt compatible inputs. devices may be test ed using any input voltage within the abov e specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density ? 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buffer) times frequency should not exceed 3,765pf/ mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications va lid for radiation dose ? 1e6 rads(si) per mil-std-883 method 1019. 8. power dissipation specified per switching output. 9. guaranteed by character ization, but not tested. p total1 power dissipation 2, 8 c l = 50pf v dd = 4.5v to 5.5v 1.0 mw/ mhz p total2 power dissipation 2, 8 c l = 50pf v dd = 3.0v to 3.6v 0.5 mw/ mhz i ddq quiescent supply current v in = v dd or v ss v dd from 3.0v to 5.5v 10 ? a ? i ddq quiescent supply current delta for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz v dd = 0v 15 pf c out output capacitance 5 ? = 1mhz v dd = 0v 15 pf
6 ac electrical characteristics for the UT54ACTS74E 2 ( v dd = 3.0v to 5.5v; v ss = 0v 1 ; -55 ? c < t c < +125 ? c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose ? 1e6 rads(si) per mil-std-883 method 1019. symbol parameter condition v dd minimum maximum unit t phl1 clk ? to q, q c l = 50pf 3.0v to 3.6v 3 30 ns 4.5v to 5.5v 3 14 t plh1 clk ?? to q, q c l = 50pf 3.0v to 3.6v 3 20 ns 4.5v to 5.5v 2 11 t phl2 pre to q c l = 50pf 3.0v to 3.6v 4 30 ns 4.5v to 5.5v 3 15 t plh2 pre to q c l = 50pf 3.0v to 3.6v 3 20 ns 4.5v to 5.5v 3 12 t phl3 clr to q c l = 50pf 3.0v to 3.6v 4 30 ns 4.5v to 5.5v 3 15 t plh3 clr to q c l = 50pf 3.0v to 3.6v 3 21 ns 4.5v to 5.5v 2 12 f max maximum clock frequency c l = 50pf 3.0v to 3.6v 100 mhz 4.5v to 5.5v 125 t su1 data setup time before clk ? c l = 50pf 3.0v to 3.6v 4 ns 4.5v to 5.5v 3 t su2 pre or clr inactive setup time before clk ? c l = 50pf 3.0v to 3.6v 1 ns 4.5v to 5.5v 1 t h data hold time after clk ? c l = 50pf 3.0v to 3.6v 0 ns 4.5v to 5.5v 0 t w1 minimum pulse width clk high or low c l = 50pf 3.0v to 3.6v 5 ns 4.5v to 5.5v 4 t w2 minimum pulse width pre or clr low c l = 50pf 3.0v to 3.6v 5 ns 4.5v to 5.5v 4
7 packaging 1. all exposed metallized ar eas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance with mil-prf- 38535. 4. dimension symbol is in accordance with mil- prf-38533. 5. lead position and colanarity are not measured. figure 1. 14-lead flatpack
ordering information: UT54ACTS74E: smd drawing number: 96535 = UT54ACTS74E device type: 02 = 1 rad(si)/sec package type: x = 14-lead ceramic botto m-brazed dual-in-line flatpack lead finish: (notes 1 & 2) a = solder c = gold x = optional 5962 ***** ** * * * * total dose: (note 3 and 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) 03 = 50 to 300 rads(si)/sec class designator: q = qml class q v = qml class v notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2. device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si), and 5e5 rads(si), and is tested in accordance w ith mil-std-883 test method 1019 condition a.
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